Reducing Leakage Power and Optimize the Area of Flip Flop Design using Stack Transistor Technique

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Year:
2018
Type of Publication:
Article
Keywords:
Stack Transistor, MOSFET, Variable Threshold, Propagation Delay, Stacking Technique
Authors:
Richa Singh; Dilip Ahirwar
Journal:
IJISM
Volume:
6
Number:
3
Pages:
99-101
Month:
May
ISSN:
2347-9051
Abstract:
In this paper, a low leakage power and area optimize CMOS logic is design and simulated without giving up its performance. The methodology is base on series connected MOSFET called as stack transistor technique. Abstractly, the reduce size series connected MOS transistor with gate terminal is connected with each other behaves line a single gate input transistor. In this paper, a CMOS layout is design and simulated in a deep submicron technology with significant reductions in power, leakage, and area of the hybrid circuits when compared with the conventional design.
Full text: IJISM_755_FINAL.pdf

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