Parametric Optimization of Clocked Redundant Flip-Flop Using Transmission Gate

Select Volume / Issue:

• Volume 4,Issue 1, Jan. 2016

Year:

2016

Type of Publication:

Article

Keywords:

Transmission Gate, Master-Slave Latch, Adaptive Couple, Short Channel Effects, Flip-flops

Authors:

Sapna Sadhwani; Dr. Rita Jain

Journal:

IJISM

Volume:

4

Number:

1

Pages:

20-24

Month:

January

ISSN:

2347-9051

Abstract:

In this paper the flip-flops circuits are designed with adaptive coupled transmission gate working on conditional precharge and the conditional capture technologies so as to reduce the redundant switching activities. The schematic level circuits are design and the parametric optimization is done at layout level. The D flip-flops in digital integrated circuit consume 50 % of area and power due to the redundant transition at the internal nodes when the input and output are at the same state. Timing simulation of transmission gate based flip flop shows the best power and delay optimization. The layout is designed using Microwind layout with 0.05 μm technology. In this paper NAND latch and Flip-flop both are discussed, also D-Flip-flops are using transmission gates are explained.

Full text: ijism-508-Final.pdf